1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more specifically, to a semiconductor memory device allowing reduction in power consumption.
2. Description of the Background Art
FIG. 10 is a schematic block diagram of a dynamic RAM (hereinafter referred to as DRAM) as an example of a conventional semiconductor memory device.
Referring to FIG. 10, a DRAM 1 includes a memory cell array portion 1, row decoders 9a and 9b, a column decoder 11, a read/write circuit 13, an address buffer 15, an address counter 17, a switch signal generating circuit 19, a /RAS input circuit 21, a /CAS input circuit 23, a data output circuit 25, a data input circuit 27, and a /WE input circuit 29. Further, DRAM 1 includes an address input terminal group 31, an external /RAS signal input terminal 33, an external /CAS signal input terminal 35, a data output terminal 37, a data input terminal 39 and a /WE signal input terminal 41.
Memory cell array portion 3 includes memory cell arrays 5a, 5b and a sense amplifier 7. Between memory cell arrays 5a and 5b, sense amplifier 7 is provided. Each of memory cell arrays 5a and 5b includes a plurality of memory cells each consisting of one transistor and one capacitor, with the memory cells arranged in a matrix. Word lines are connected to respective memory cells in the row direction, and bit lines are connected to respective memory cells in the column direction.
To /RAS input circuit 21, an external /RAS signal is input through external /RAS signal input terminal 33, and an output therefrom is applied to an address counter 17, address buffer 15 and switch signal generating circuit 19. To /CAS input circuit 23, an external /CAS signal is input through external /CAS signal input terminal 35, and an output therefrom is applied to address counter 17 and address buffer 15.
An output from address counter 17 is applied to address buffer 15. To address buffer 15, address signals A0 to An from address input terminal group 31 are also applied. Address buffer 15 applies a row address RA to each of row decoders 9a and 9b, and to switch signal generating circuit 19. Further, address buffer 15 applies a column address CA to column decoder 11.
Row decoder 9a selects a word line WL of memory cell array 5a in accordance with row address RA1, and row decoder 9b selects a word line WL of memory cell array 5b in accordance with row address RA2. Column decoder 11 selects (a pair of) bit lines BL of memory cell arrays 5a and 5b, respectively, in accordance with column address CA. The selected bit lines BL are connected to an I/O line. The I/O line is connected to read/write circuit 13. To read/write circuit 13, an output from data input circuit 27 is applied, and an output from read/write circuit 13 is applied to data output circuit 25. An output from /WE input circuit 29 are applied to data output circuit 25 and data input circuit 27.
A write enable /WE signal from /WE signal input terminal 41 is applied to /WE input circuit 29. Therefore, /WE input circuit 29 applies a write enable /WE signal for writing, especially, to data input circuit 27, and data input circuit 27 applies data input through data input terminal 39 to read/write circuit 13. By contrast, /WE input circuit 29 operates to apply the read data, which has been applied from read/write circuit 13 to data output circuit 25, to data output terminal 37.
FIG. 11 is a schematic diagram of the sense amplifier shown in FIG. 10, and FIG. 12 is a schematic diagram of the switch signal generating circuit of FIG. 10.
Referring to FIG. 11, sense amplifier (SA) 7 includes N channel MOS transistors (hereinafter referred to as NMOS) Q5, Q6, Q7 and P channel MOS transistors (hereinafter referred to as PMOS) QS, Q9 and Q10. Sense amplifier 7 is connected to bit line pair BL1, /BL1 of memory cell array 5a through connection transistors Q1 and Q2, and connected to bit line pair BL2, /BL2 of memory cell array 5b through transistors Q3, Q4. Connection transistors Q1, Q2, Q3 and Q4 are NMOSs. Such a structure in which two sets of bit line pairs are connected to a set of sense amplifiers through connection transistors is referred to as a shared sense amplifier configuration. The shared sense amplifier type sense amplifiers have come to be used in recent DRAMs having large capacities.
A memory cell MC1 including one transistor and one capacitor is connected to bit line BL1 and word line WL1, and a memory cell MC2 is connected to bit line BL2 and word line WL2. Sense amplifier 7 writes, stores and reads data to and from such memory cells MC1 and MC2. For enabling reading or the like, it is necessary that bit line pair BL1, /BL1 or bit line pair BL2, /BL2 is connected to sense amplifier 7.
Accordingly, a control signal .phi.1 is connected to control electrode of each of connection transistors Q1 and Q2, and control signal .phi.2 is applied to a control electrode of each of connection transistors Q3 and Q4.
In order to write data without fail to each of the memory cells MC1 and MC2, sense amplifier 7 must transmit a signal which has been amplified to the level of a power supply potential through connection transistors Q1, Q2, Q3 and Q4 to memory cells MC1 and MC2, without lowering the potential. Since connection transistors Q1, Q2, Q3 and Q4 are formed of NMOSs, it is necessary that control signals .phi.1 and .phi.2 input to connection transistors are boosted to be higher than the level of the power supply potential.
Therefore, switch signal generating circuit 19 includes a charge pump circuit 103 and a charge pump circuit 107, as shown in FIG. 12. Further, switch signal generating circuit 19 includes inverters 101a, 101b, 101c, an oscillating circuit 105, PMOSs 109a, 109b, NMOSs 111a, 111b, and an NAND gate 113.
Charge pump circuit 103 operates in response to an external /RAS input from /RAS input circuit 21. Charge pump circuit 107 continuously operates in response to a signal .phi..sub.C output from oscillating circuit 105. Charge pump circuits 103 and 107 generate a boosting signal .phi..sub.H. The boosting signal .phi..sub.H is output as a control signal .phi..sub.1 or .phi..sub.2 through PMOS 109b.
More specifically, dependent on the signal level of external /RAS and row address RA, NAND gate 113 outputs a signal at a logic high level. Therefore, NMOS 111a turns on and NMOS 111b turns off. Through NMOS 111a, a signal of a logic low level, which is ground potential, is applied to the control electrode of PMOS 109b, and PMOS 109b turns on. Therefore, boosting signal .phi..sub.H is applied to the control electrode of PMOS 109a through PMOS 109b, so that PMOS 109a turns off. Further, boosting signal .phi..sub.H is output as control signal .phi..sub.1 or .phi..sub.2 through PMOS 109b.
In this manner, control signal .phi..sub.1 (.phi..sub.2) is generated in accordance with the address signal RA applied to NAND gate 113.
FIG. 13 is a time chart showing signals required in the sense amplifier of FIG. 11 and the switch signal generating circuit of FIG. 12, in which (a) shows the waveform of external /RAS, (b) shows the waveform of signal .phi..sub.C output from the oscillating circuit, (c) is a waveform of boosting signal .phi..sub.H, (d) shows waveforms of row addresses RA1 and RA2, (e) shows waveforms of control signals .phi..sub.1 and .phi..sub.2 applied to the connection transistor, (f) shows states of word lines WL1 and WL2, (g) shows states of bit line pairs BL1 and /BL1, and (h) shows states of bit line pairs BL2, /BL2.
The operation of the circuit shown in FIGS. 11 and 12 will be described with reference to FIG. 13.
First, even when external /RAS is at the high (H) level (standby state), oscillating circuit 105 operates. Therefore, charge pump circuit 107 is generating a boosting signal .phi..sub.H of the boosted level.
When external /RAS changes to the L level, row address RA1 (RA2) is taken. For example, in FIG. 13, row address RA1 is at the H level, and thus word line WL1 is selected. Therefore, bit line pair BL2, /BL2 sharing sense amplifier 7 with bit line pair BL1, /BL1 must be separated from sense amplifier 7. Accordingly, control signal .phi..sub.2 is at the L level.
Thereafter, word line WL1 is selected and attains to the H level. Therefore, data in memory cell MC1 is read to bit line BL1, and sense amplifier 7 amplifies potential difference between bit lines BL1 and /BL1.
In this manner, access is allowed when external /RAS attains to the L level. Thereafter, external /RAS signal attains to the H level and word line WL1 attains to the L level. At this time, data amplified by sense amplifier 7 is again written to memory cell MC1. This operation is referred to as restore operation.
Then, control signal .phi..sub.2 changes from the L level to the H level, and connection transistors are all set to the standby state.
Recently, memories of large storage capacity have come to be widely used in portable equipments. Power consumption in accessing the memories has been decreased, and especially a DRAM having self refresh function for reducing power consumption while data is retained has been developed. Here, the self refresh function refers to a function in which data of all the memory cells are successively refreshed automatically in the chip of the DRAM when an input sequence satisfying a prescribed condition is externally applied, allowing data retention.
FIG. 14 is a schematic block diagram of a DRAM having such a self refresh function, and FIG. 15 is a block diagram showing the self refresh signal generating circuit and the internal /RAS generating circuit shown in FIG. 14.
Referring to FIG. 14, portions different from the DRAM 1 of FIG. 10 will be mainly described. The DRAM 151 shown in FIG. 14 further includes a self refresh signal generating circuit 153 and an internal /RAS generating circuit 155. To self refresh signal generating circuit 153, an external /RAS is input through external /RAS signal input terminal 33, and an external /CAS signal is input through external /CAS signal input terminal 35. Based on these two signals, self refresh signal generating circuit 153 applies a self refresh signal .phi..sub.SELF to /RAS input circuit 21 and internal /RAS generating circuit 155. Based on the applied self refresh signal .phi..sub.SELF, internal /RAS generating circuit 155 generates internal (int) /RAS and applies this signal to /RAS input circuit 21.
Self refresh signal generating circuit 153 and internal /RAS generating circuit 155 are structured as shown in FIG. 15. More specifically, self refresh signal generating circuit 153 and internal /RAS generating circuit 155 includes a CBR (/CAS before /RAS) detecting circuit 201, a timer circuit 203, an oscillating circuit 205 and a frequency dividing circuit 207. External /RAS and external /CAS are input to CBR detecting circuit 201, and an output from this circuit is applied to timer circuit 203. To timer circuit 203, the signal .phi..sub.C which is an output from oscillating circuit 205 is also applied, and self refresh signal .phi..sub.SELF is Output from timer circuit 203. Self refresh signal .phi..sub.SELF is applied to frequency dividing circuit 207, and frequency dividing circuit 207 outputs internal /RAS based on the signal .phi..sub.C which is the output from oscillating circuit 205, and on the self refresh signal .phi..sub.SELF.
FIG. 16 is a diagram of waveforms showing the operation of the self refresh signal generating circuit and the internal /RAS generating circuit shown in FIG. 15, in which (a) shows external /RAS, (b) shows external /CAS, (c) shows the signal .phi..sub.C, (d) shows the self refresh signal .phi..sub.SELF, (e) shows internal /RAS and (f) shows control signals .phi..sub.1 and .phi..sub.2.
Referring to FIG. 16, at the time of self refresh, external /CAS changes from the H level to the L level before external /RAS changes from the H level to the L level. This is detected by CBR detecting circuit 201. Based on the result of detection, timer circuit 203 operates.
Thereafter, when the period in which external /RAS is at the L level and external /CAS is at the L level exceeds a prescribed time period, timer circuit 203 generates a self refresh signal .phi..sub.SELF.
Then, as the self refresh signal .phi..sub.SELF is generated, frequency dividing circuit 207 generates internal /RAS signal in every prescribed period obtained by frequency-dividing the oscillation signal .phi..sub.C. Refreshing is performed intentionally, by internal address counter 17.
In such a DRAM 151 that has the self refresh function, switch signal generating circuit 19 generates control signal .phi..sub.1 or .phi..sub.2 as internal /RAS attains to the L level, and thereafter restore operation takes place.
However, since control signal .phi..sub.1 (.phi..sub.2) is generated once in every 1 cycle in which external /RAS or internal /RAS changes its level, the switch signal generating circuit consumes the voltage of the boosting signal .phi..sub.H in order to charge the control electrode of connection transistors. In order to compensate for this consumed voltage, charge pump circuit 103 operates in response to external /RAS signal or internal /RAS signal, to charge the boosting signal .phi..sub.H. This prevents lowering of the potential level.
However, if the cycle time of external /RAS signal or internal /RAS is long, the level of the boosting signal .phi..sub.H lowers because of leak current. Because of this lowering of the level, it is possible that the signal amplified by the sense amplifier is not adequately written to the memory cell in restore operation. This may lead to shortened data storage time. In order to cope with this problem, the charge pump circuit which operates continuously is provided, so that the boosting signal .phi..sub.H is boosted periodically to prevent level lowering.
However, since the charge pump circuit which continuously operates is provided, there is considerable power consumption.